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| IPSCC |
| Introduction |
| The IPSCC Board is a double height
Industry Pack Bus Interface Board that performs the function of encoding/decoding of
serial data. The Board is fully compliant with the Industry Pack Bus Specification
endorsed by Green Springs Computers and will functionally perform in any Industry Pack
Host Carrier Board. The specific function of the board is to interface to the EAI
Sub-Channel Racks through differential serial links. The IPSCC Board uses standard
off-the-shelf components and has been designed using reliable and robust Surface Mount
Technology. |
| IPSCC Block Diagram [Schematic
Sheet 1] |
| The IPSCC Block diagram consists of
the control logic in PALs that implements an IP-A Interface and IP B Interface Control
since the board is a double-height IP Board. This Control Logic consists of I/O Decoders
that permits access to the various devices like the input registers, output shifters, ID
ROM, Status port and some registered logic to permit the introduction of wait states for
devices that require a longer IP Bus Access for proper operation. |
| Parallel Data is output serially by
encoding data in a serial format by parallel-to-serial shift register logic. This is
commonly denoted in the block diagram as the Serializer. |
| Input Serial Data is reconstructed by
Decoder circuitry that converts the serial data back into a parallel format which can then
be read out by the IP Host from parallel data registers. |
| The Serial I/O Data interfaces
physically to the EAI Sub-Channel Racks with the help of RS-422/RS485 Drivers/Receivers
which implement the required EIA Specification. |
| IPSCC Serial Receiver Decoding
Logic [Schematic Sheet 2] |
| U27 is a DS1000M-100 Silicon delay
line with tap delays of 20ns. R40, R60 and R80 are 40ns, 60ns and 80ns delayed versions of
RDATA which is the raw serial data coming in from the RS-422/RS485 Serial Receivers. |
| U21 is a DS1000-200 Silicon delay line
with tap delays of 40ns. It is used to generate DRCLK and a 160ns delayed version of RCLK
which is used to correctly detect mid-cell transition is a 300ns width pulse. |
| U28 is the IPSCC Receive Decoder PAL.
More details on its operation is given in the section on IPSCC PAL Explanations. |
| U26B is a 74ACT74 flip-flop that is
used to generate RCLK while U26B, also a 74ACT74 flip-flop is used to generate SBUFIN the
data-in signal to the serial shifters. |
| U29 is a 74HCT161 configured to
implement up-counting. The size of the serial input frame is 16-bits and the 74HCT161
counts 16 occurrences of RCLK. Note that the counter is enabled by REN only when the
detection of a start bit of the receive frame has occurred. Every new Digital Input
mandates the requirement of resetting the 74HCT161 Counter by asserting SCLEAR\. |
| SBUFIN is the serial data input that
has been reconstructed from the serial input clock data. It is input to a 74HCT164(U30)
shift register which is clocked by RCLK, and is cascaded with another 74HCT164 shift
register to form a 16-bit shift register. After 16 RCLKs the serial data is shifted into
the cascaded 16-bit shift register. DEL_RLOAD\ is then asserted to load the serial data
into the two 74HCT374 8-bit registers. This data can now be read by the host CPU via the
IP Bus Interface by the assertion of SDIN\ during a data read cycle. |
| IPSCC Serial Transmit Encoder
Logic: [Schematic Sheet 3] |
| U24 and U35 are two 74HCT166
parallel-to-serial 8-bit shift registers that have been cascaded to form a 16-bit parallel
to serial shift register. Serial Command or Serial Data is loaded into these shift
registers by a 16-bit write from the host CPU over the IP Bus Interface. LDXSR\ is the
signal that loads the value into the serial shifters. XCLK1 is the shift-out clock. XCLK1
has a 300ns cycle time. |
| U31 is a 74HCT161 binary counter that
counts 16 XCLK1 occurrences. It is enabled for counting by XEN which is asserted only
after the first start bit has been generated. SCLEAR\ is used to clear this counter. |
| X1 is a 13.36MHz crystal oscillator
that is used along with U36 the Transmit Encoder Pal to generate XCLK1. DUALXC and DUALXD
are versions of XCMD and XDATA respectively with half the cycle time. They are divided by
two in U22A and U22B respectively to give cycle times of 300ns. U20A is used to buffer
these signals to give the actual XCMD and XDATA signals that go to the SN75113
RS-422/RS485 Drivers. |
| U32 is the Transmit Control Pal. Look
at the PAL Equations for more detailed information |
| Serial Differential
Transmitter Interface [Schematic Sheet 4] |
| SN75113 Differential RS-422/RS485
Transceivers are used to drive serial data from the IPSCC Board to the EAI Sub-Channel
Racks. Four such devices are used to drive Serial Command Information to the EAI
Sub-Channel Racks. Command information driven over all the eight pairs of lines SCP[1..8]
and SCM[1..8] are identical as these four ICs (U3,U4,U7 & U12) all have the same XCMD
signal as their input. Only the appropriate EAI Sub-Channel Rack whose address information
is encoded in the serial command pattern will respond. |
| Another set of four such differential
transceivers is used to drive the Serial Data information over eight pairs of serial data
lines SDP[1..8] and SDM[1..8]. Data driven over all eight pairs is also identical as all
these four ICs (U6,U10,U14 & U17) have XDATA as their input. Only the EAI Sub-Channel
whose address information was encoded in the Serial Command output prior to the Data Out
write will accept data written out serially over these lines. Note that these transceivers
are enabled only when data is to be output to the EAI Sub-Channel racks. This is done by
using the DOUTEN signal as an enable control for these Serial Data Transceivers. |
| RP1, RP2, RP3 and RP4 are 68ohm pull
up resistor packs and are used to terminate reflections on the physical serial lines by
terminating the lines in their characteristic impedance. |
| Serial Differential Receiver
Interface: [Schematic Sheet 5] |
| Eight pairs of differential serial
inputs are received by the SN75115 RS-422/RS485 Differential Receiver ICs. All the outputs
of the SN75115 devices are tied to a single line to form a signal called RDATA. The idea
behind this is that at any given moment in time only one of the serial input pairs can be
active, as the serial communication protocol is similar to a query-response mechanism.
This then requires the use of only a single Receiver Decode Logic block. RDATA is the
input serial signal from which data is recovered. RDATA is pulled up by a 68 ohm resistor. |
| Industry-Pack Bus Interface
Logic: [Schematic Sheet 6] |
| U1 is a 82S123 bipolar PROM that
contains Industry Pack Bus related information and can be accessed by character (byte)
reads to the Industry Pack ID Address Space Address. A maximum of 32 bytes is provided for
in the Industry Pack Bus Specification. |
| U2 is a 74FCT240 that is used as a
status port. The following are the different status supported. |
- LOOPBACK MODE Bit 0 (D0)
- DMA Channel 0 Bit 1 (D1)
- DMA Channel 1 Bit 2 (D2)
- DMA Channel 2 Bit 3 (D3)
- Rx Timeout Bit 4 (D4)
|
| Digital Receive Timeout Logic is
basically a set of six 4-bit binary counters implemented using 74HCT393 devices. The
counters are enabled just before the Serial Command Request is given for a Digital Input,
by the assertion of EN-TO\. The counters are clocked by Industry Pack Bus CLK which is an
8MHz signal. If a reply occurs by the reception of a serial frame then EN-TO\ is negated
clearing the 74HCT393 counters else DIN-TO is driven high indicating that a Digital Input
Timeout has occurred. |
| U5 is a PAL22V10-15 device. It is used
to implement DMA Control on the IP Bus Interface. Additionally it is also responsible for
the generation of ACK1\ the access acknowledge signal for the IP-A Bus Interface and
EN-TO\ the signal that enables the Digital Timeout Logic. |
| U9 is a PAL22V10-15 device. It is used
to implement general I/O decoding for the IP-A Bus Interface. U13 is a PAL20V8-25 device
that is used to implement the IP-B Bus Interface I/O Decoder and Control. U13 is
responsible for the generation of ACK2\, the access acknowledge signal for the IP-B Bus
Interface. |
| For more information on the functions
performed by these PALs please refer to the relevant PAL Equations files. |
| IPSCC Power Supply Capacitors
& Connectors: [Schematic Sheet 7] |
| C1,C4,C5,C28,C29,C39 are SMT 6.8ufd
tantalum capacitors used for power supply decoupling. All other capacitors are 0.1ufd
devices and are used for high frequency filtering of power supply noise. |
| P1 is a D-Shell type IP-A Bus
Interface Connector and hosts all signals relevant to the IP-A Bus Interface. |
| P3 is a D-Shell type IP-B Bus
Interface Connector and hosts all signals relevant to the IP-B Bus Interface. |
| P2 is the I/O Interface Connector for
the Serial I/O Lines on IP-A Side of the interface. P4 is a connector that is present but
is however not being used. It only provided mechanical stability for mounting to the host
IP Carrier. |
| Industry Pack Serial Interface Controller Address Map |
| Introduction |
| All address decoding is performed in
PALs. The following table gives the offsets from the base addresses of the Industry Pack
Host Carrier base addresses for ID Address Space, I/O Address Space and Interrupt Address
Space for the IP-A, IP-B, IP-C and IP-D slots of the Industry Pack Interface. |
| Signal Details |
Read/Write |
A6 |
A5 |
A4 |
Hex Offset |
| Status Read (STATCS\) |
Read |
0 |
0 |
0 |
0x00 |
| Reset CMDMODE (RSTCMDMODE\) |
Read |
0 |
0 |
1 |
0x10 |
| Generate First Cmd (GENDRQC\) |
Write |
1 |
0 |
x |
0x40 |
| Assert SCLEAR\ |
Read |
1 |
1 |
0 |
0x60 |
| Negate SCLEAR\ |
Read |
0 |
0 |
1 |
0x10 |
|
| IP-A ID ROM Address Space |
| The IPSCC ID ROM is located at ID
Space starting at address 0x00. |
| IP-B I/O Address Space |
| Signal Details |
Read/Write |
A2 |
A1 |
Hex Offset |
| Set Loop Back (LPBK\) |
Write |
0 |
0 |
0x00 |
| Reset Loop Back (RSTLPBK\) |
Read |
0 |
0 |
0x00 |
| Set Command Mode (CMDMODE\, SXWR\) |
Write |
0 |
1 |
0x02 |
| Write DOUT (SXWR\) |
Write |
1 |
0 |
0x04 |
| Read DIN Data (SDIN\) |
Read |
1 |
0 |
0x04 |
|
| Description
of PALS on IPSCC CPU Board |
| PAL Control Logic Introduction |
| The IPSCC board uses Programmable
Array Logic (PALs) to generate the different control signals required by the different
logical modules. In all six PAL devices are used on the IPSCC Board. |
| The following is a list of the PAL
device files used and their function. The PAL equations should be edited in a pure ASCII
text editor. Currently the files have an *.PDS extension and are compiled using Advanced
Micro Devices PALASM2 v2.23D. |
- IPSCC1.PDS - Serial Receive Decoder Control Logic
- IPSCC2.PDS - Serial Transmit Control Logic
- IPSCC3.PDS - Serial Transmit Encoder Control Logic
- IPSCC4.PDS - IP-A Bus I/O Decoder Control Logic
- IPSCC5.PDS - IP DMA Control Logic
- IPSCC6.PDS - IP-B Bus I/O Decoder Control Logic
|
| Description of IPSCC1 PAL (U28) |
| Input Signals of IPSCC1 |
- RCLK is the receive clock signal. It
is generated by U26A/5 only when the start bit cell transition is detected on a receive
frame. It is used to register/clock the REN, RDONE and DEL_RLOAD\ signals in the PAL.
- R40 is a 40ns delayed version of
RDATA, the serial data received from the RS-422/RS485 differential receivers. It is used
in the generation of the SETDIN\ and SETRCLK\ signals.
- R60 is a 60ns delayed version of
RDATA, the serial data received from the RS-422/RS485 differential receivers. It is used
in the generation of SETRCLK\.
- DOUTEN\ signal is the data
output enable signal that permits the XDATA differential RS-422/RS485 drivers to be
enabled, permitting serial data to be written out to the EAI Sub-channel Racks.
- SCLEAR\ signal is used to clear any
registered logic before the reception of a Rx frame.
- RDATA is the serial data received
from the RS-422/RS485 differential receivers. It is used to generate SETDIN\.
- LPBK\ signal is an I/O decode from
the IP-B I/O decoder that latches itself. It is used to put the Serial I/O Logic in
internal loopback mode, where the data that is output on the XDATA lines is internally
looped back to form RDATA. This is a useful tool for diagnostics.
- CR[0...3] - These are the count bits
of the 74HCT161 (U23) . They are used in the generation of RDONE\ and DEL_RLOAD\. These
inputs indicate when a 16-bit frame has been received.
- DRCLK is a 40ns delayed version of
RCLK and is used in the generation of SETDIN\ and to block the generation of SETDIN\.
- SBUFIN signal is used to enable REN.
It gets set active on the detection of the first mid-cell transition. (Start bit) . Once
active REN gets latched and subsequent toggles of SBUFIN make no impact on the state of
REN till the entire 16-bit frame is received.
|
| Output Signals of IPSCC1 |
- SETDIN\ output is used to
preset the 74ACT74 (U26B) flip-flop. It is asserted when one of the serial input data bits
is a one. The assertion of SETDIN\ is blocked if DOUTEN\ is active indicating that the
data being seen on RDATA is actually an output data frame. Only assertion of LPBK\
overrides this.
- SETRCLK\ output is used to
preset the 74ACT74 (U26A) flip-flop. It is asserted by the zeroing of R40 and R60 inputs
provided DRCLK is inactive. Thus this signal is used for generating the receive clock
signal RCLK.
- REN signal is the 74HCT161 (U23)
counter enable control signal. It is generated only after the first start bit clock cell
detection has been completed. It is synchronous to RCLK and is disabled by RDONE\. It is
enabled only for Serial Data In by being blocked if DOUTEN\ is active. LPBK\ assertion can
override this.
- DEL_RLOAD signal is generated when
16-bits have been received in the Rx frame as indicated by CR[0..3] all going active. It
is synchronous to RCLK and is generated on the next rising edge of RCLK.
- DEL2LOAD is a single PAL propagation
delay version of DEL_RLOAD.
- RLOAD is a single PAL propagation
delay version of DEL2LOAD.
- RDONE\ output signal indicates that
reception of a Serial Input Data frame has been completed. It is synchronous to RCLK and
is reset by SCLEAR\ assertion. It is enabled only for Serial Data In by being blocked if
DOUTEN\ is active. LPBK\ assertion can override this.
|
| Description of PAL IPSCC2 (U36) |
| Input Signals of IPSCC2 |
- SCLK75 is a 72ns clock signal input.
It is generated by the 13.36MHz crystal oscillator.
- SBUFOUT is the Serial Data Out
signal. It is the output of the serial shift out register 74HCT166 (U35). It is used in
the formation of DUALXC and DUALXD outputs.
- XEN is the Serial Transmitter Enable
control signal.
- MDMODE\ is the signal that indicates
the Serial Command Mode is active.
- LDXSR\ input signal is output from
the transmit control PAL. It is the signal that loads the transmit shift registers U24 and
U35.
- DOUTEN\ is the Serial Data output
enable signal that permits the XDATA differential RS-422/RS485 drivers to be enabled,
permitting serial data to be written out to the EAI Sub-channel Racks.
- LCMDMODE\ is a latched version of
the CMDMODE\ signal.
|
| Output Signals of IPSCC2 |
- CLK150 output signal is a divide by
two of the SCLK75 signal. It is used in the formation of XCLK1 and is not used externally.
- CLK300 output signal is a divide by
four of the SCLK75 signal. It is used in the formation of XCLK1 and is not used
externally.
- XCLK1 is a 50% duty cycle 300ns
cycle time clock signal. It is the Serial Transmitter Logic Clock.
- XCLK2 is a 50% duty cycle 300ns
cycle time clock signal. It is an inverted version of XCLK1 and is not used externally.
- DUALXC is 150ns output signal that
has the Serial Command Data encoded along with it. DUALXC is asserted only after the
Serial Command Data has been latched into the Serial Output shift registers. It is active
at all times and when Serial Data information is not encoded as a part of it, it just
reflects the XCLK1 signal.
- DUALXD is 150ns output signal that
has the Serial Output Data encoded along with it. DUALXD is asserted only after the Serial
Output Data has been latched into the Serial Output shift registers. It is active only
when LCMDMODE\ is active and when Serial Data information is not encoded as a part of it,
it just reflects the XCLK1 signal.
|
| Description of PAL IPSCC3 (U32) |
| Input Signals of IPSCC3 |
- XCLK1 is the 300ns cycle time Serial
Transmitter clock signal.
- SXWR\ is the Serial Command &
Serial Data Write strobe signal. It is generated by the IP-B I/O Decoder PAL.
- D14 is the D14 Industry Pack data
bus line. It must be low in order for a Serial Command Write to be recognized by the EAI
Sub-channel Racks as a Serial Data Output Command. If it is high during a Serial Command
Write the command is decoded by the EAI Racks to be a Serial Data Input Command.
- CX[0..3] are the count bits of the
74HCT161 (U31) . They are used in the generation of XDONE\ and XEN signals. These inputs
indicate that a 16-bit frame has been transmitted.
- CMDMODE\ is the signal that
indicates the Serial Command Mode is active. It is used in the generation of the LCMDMODE\
signal.
- SCLEAR\ signal is used to clear any
registered logic before the transmission of a Serial Tx frame.
|
| Output Signals of IPSCC3 |
- S1_SXWR\ is a one XCLK1 delayed
version of SXWR\.
- S2_SXWR\ is a two XCLK1 delayed
version of SXWR\.
- SXWRDONE\ is synchronized to XCLK1
and is generated on the rising edge of the clock that detects both SXWR\ and S2_SXWR\
active.
- LDXSR\ is the strobe to load the
transmit shift output registers U24 and U35. It is synchronous to XCLK1 and is a single
XCLK1 pulse wide. It is asserted when S1_SXWR\ is asserted and S2_SXWR\ is inactive.
- XEN is the 74HCT161 Tx shift counter
(U31) enable signal. It is synchronous to XCLK1 and is generated on the XCLK following
LDXSR\ deassertion. It is cleared by SCLEAR\ and XDONE\.
- DOUTEN\ is the signal that enables
the Serial Data Output RS-422/RS485 differential transceivers. It is asserted by assertion
of CMDMODE\ as long as D14 is low. It then is latched and is reset only by SCLEAR\ or a
new Serial Command.
- XDONE\ is the Serial Transmit Done
signal. It is synchronous to XCLK1 and is asserted on the XCLK1 occurrence following the
15th XCLK after the start of transmission of the frame provided SCLEAR\ is inactive.
- LCMDMODE\ signal is used in a
different manner during PC/104 snoop mode. In this case the signal controls the 74LS646
(U38,U39) to act as input. This is a latched version of CMDMODE\. It is synchronous to
XCLK1, latches itself and is not reset until either Serial Transmit done XDONE\ is
asserted or SCLEAR\ is asserted.
|
| Description of PAL IPSCC4 (U9) |
| Input Signals of IPSCC4 |
- A1,A4,A5,A6 are the address lines of
the IP-A Bus Interface and are used in the implementation of the I/O Decoders in the PAL.
- IDSEL1\ is the ID Prom Select Line
for IP-A Industry Pack Bus Interface.
- IOSEL1\ is the I/O Address Space
Select Line for the IP-A Industry Pack Bus Interface.
- MEMSEL1\ is the Memory Address Space
Select Line for the IP-A Industry Pack Bus Interface.
- INTSEL1\ is the Interrupt
Acknowledge Space Select Line for the IP-A Industry Pack Bus Interface.
- R/W\ is the Read/Write strobe for
the IP-A Industry Pack Bus Interface.
- DMACK1\ is the DMA Acknowledge
signal for the IP-A Industry Pack Bus Interface.
- DMACK2\ is the DMA Acknowledge
signal for the IP-B Industry Pack Bus Interface.
- ACK1\ is the cycle terminate
(acknowledge signal) for IP-A Industry Pack Bus Interface. It is used to introduce wait
states for those devices that require additional wait states.
- IOSEL2\ is the I/O Address Space
Select Line for the IP-B Industry Pack Bus Interface.
- RESET\ is the Industry Pack
Bus Interface RESET signal and is used to set all logic on the IPSCC Board to a known
state.
|
| Output Signals for IPSCC4 |
- SCLEAR\ is a CLEAR signal that is
used to reset various flip-flops, latched outputs in the different PALs, reset the
different counters etc. It is generated during a read cycle to the IP-A I/O Address
Space.. It is a latched output and is reset by RSTCMDMODE\.
- GENDRQC\ is the signal that is used
to generate the first DMA request on DMAREQ1. It is generated on a read cycle to the IP-A
I/O Address Space.
- IDROMCS\ is the signal that
generates the ID PROM (U1) chip select signal. It is generated on a read to the IP-A ID
ROM Address Space. It is also generated by the other IP-A I/O addresses to be used in the
generation of ACK1\.
- STATCS\ is the status port chip
select signal. It is generated on a read to the IP-A I/O Address Space. It is latched and
reset by the occurrence of ACK1\, RESET\ or SCLEAR\.
- RSTCMDMODE\ is the reset command
mode signal. It is generated on a read to the IP-A I/O Address Space. It is also reset
automatically in response to service from DMA; DMACK1\ and DMACK2\.
|
| Description of PAL IPSCC5 (U5) |
| Input Signals of IPSCC5 |
- CLK is the Industry Pack Bus 8MHz
clock signal.
- GENDRQC\ is the Generate DMA request
signal. It is used in the generation of DMAREQ0\ and WAIT1\, which is used to generate
ACK1\.
- CMDMODE\ is the Serial Transmit
Command Mode signal.
- DOUTEN\ is the signal that enables
the Serial Data Output RS-422/RS485 differential transceivers. It is asserted by assertion
of CMDMODE\ as long as D14 is low. It then is latched and is reset only by SCLEAR\ or a
new Serial Command.
- SCLEAR\ is a CLEAR signal that is
used to reset various flip-flops, latched outputs in the different PALs, reset the
different counters etc. It is generated during a read cycle to the IP-A I/O Address
Space.. It is a latched output and is reset by RSTCMDMODE\. It is used to clear DMAREQ0\,
DMAREQ1\ and DMAREQ2\.
- XDONE\ is the Serial Transmit DONE
signal. It is used in the generation of DMAREQ0\ and DMAREQ1\.
- RDONE\ is the Serial Receive DONE
signal. It is used in the generation of DMAREQ0\ and DMAREQ1\ signals.
- SDIN\ is the Serial Data In Read
chip select signal. It is used to reset the DMAREQ2\ signal.
- SXWR\ is the Serial Command/Serial
Data Write strobe. It is used to reset DMAREQ0\ and DMAREQ1\ signals.
- LPBK\ is the internal loopback latch
signal. It is used in the control of DMAREQ0\, DMAREQ1\ and DMAREQ2\ signals.
- STATCS\ is the status port chip
select signal. It is used to generate a wait state for an access to the status port.
- DMAEND\ is the DMA cycle over signal
which is output by the IP-A Industry Pack Bus Interface.
- S2_SXWR\ is a two XCLK1 delayed
version of SXWR\ and is used in the generation of WAIT2\.
|
| Output Signals of IPSCC5 |
- DMAREQ0\ is a DMA request signal for
the DMA Channel 0 on the IP-A Industry Pack Bus Interface. It is generated either by the
occurrence of GENDRQC\, XDONE\ or RDONE\ and gets latched. It is then cleared when the
cause for generation is serviced, the occurrence of SCLEAR\ or DMAEND\ assertion.
- DMAREQ1\ is a DMA request signal for
the DMA Channel 1 on the IP-A Industry Pack Bus Interface. It is generated either by the
occurrence of XDONE\ and gets latched. It is then cleared when the cause for generation is
serviced, the occurrence of SCLEAR\ or DMAEND\ assertion.
- DMAREQ2\ is a DMA request signal for
the DMA Channel 1 on the IP-B Industry Pack Bus Interface. It is generated either by the
occurrence of XDONE\ or RDONE\ and gets latched. It is then cleared when the cause for
generation is serviced, the occurrence of SCLEAR\ or DMAEND\ assertion, or SDIN\
assertion.
- WAIT1\ is synchronous to the
Industry Pack Bus Interface clock. It is generated on the rising edge of the CLK signal
when an access is made to the IP-A ID PROM Address Space, GENDRQC\ assertion or STATCS\
assertion.
- WAIT2\ is generated on the rising
edge of CLK with both S2_SXWR\ and SXWR\ active.
- ACK1\ is synchronous to the Industry
Pack Bus Interface clock CLK. It is generated on the rising clock edge of CLK following
the assertion of WAIT1\
|
| Description of PAL IPSCC6 (U13) |
| Input Signals of IPSCC6 |
- CLK is the Industry Pack Bus 8MHz
clock signal.
- A1,A2 are the address lines of the
IP-B Bus Interface and are used in the implementation of the I/O Decoders in the PAL.
- IDSEL2\ is the ID Prom Select Line
for IP-B Industry Pack Bus Interface.
- IOSEL2\ is the I/O Address Space
Select Line for the IP-B Industry Pack Bus Interface.
- MEMSEL2\ is the Memory Address Space
Select Line for the IP-B Industry Pack Bus Interface.
- INTSEL2\ is the Interrupt
Acknowledge Space Select Line for the IP-B Industry Pack Bus Interface.
- READ is the Read/Write strobe for
the IP-B Industry Pack Bus Interface.
- DMACK1\ is the DMA Acknowledge
signal for the IP-A Industry Pack Bus Interface.
- DMACK2\ is the DMA Acknowledge
signal for the IP-B Industry Pack Bus Interface.
- RSTCMDMODE\ is the signal used to
reset the CMDMODE\ signal..
- IOSEL1\ is the I/O Address Space
Select Line for the IP-A Industry Pack Bus Interface.
- RESET\ is the Industry Pack
Bus Interface RESET signal and is used to set all logic on the IPSCC Board to a known
state
|
| Output Signals for IPSCC6 |
- LPBK\ is the signal that is used to
do an internal loopback. It is generated on an I/O write of the I/O Address Space of the
IP-B Industry Pack Bus Interface.
- RSTLPBK\ is the signal that is used
to do reset the internal loopback signal LPBK\. It is generated on an I/O read of the I/O
Address Space of the IP-B Industry Pack Bus Interface.
- CMDMODE\ is the Serial Command Mode
write signal. It is generated on an I/O write of the I/O Address Space of the IP-B
Industry Pack Bus Interface. It is latched and is only cleared by either SCLEAR\ or
RSTCMDMODE\.
- SDIN\ is the Serial Data Input read
strobe. It is generated on an I/O read of the I/O Address Space of the IP-B Industry Pack
Bus Interface. It is also asserted by DMACK2\.
- SXWR\ is the Serial Data Output
write strobe. It is generated on an I/O write of the I/O Address Space of the IP-B
Industry Pack Bus Interface. It is latched and cleared only by ACK2\ or RESET\.
- ACK2\ is the cycle terminate (
acknowledge signal) for IP-B Industry Pack Bus Interface. It is used to introduce wait
states for those devices that require additional wait states. Additional wait states are
generated during SXWR\ in order to make sure that the data hold time for data being
written into the output shift registers is met.
|
|
